FPGA validation Engineer
Location: Beijing　
Requirement:
1)　　　　　　Knowledge of IC design and verification methodology, familiar to Verilog HDL development
2)　　　　　　Good experience with EDA tools, simulator, verification tools
3)　　　　　　Knowledge of computer architecture is plus
4)　　　　　　FPGA development experience
5)　　　　　　Chip level functional validation
6)　　　　　　6-Month Internship at least

Salary：
￥200/Day

有兴趣的同学可以把简历发至 Maggie.dai@analog.com